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Freescale Semiconductor Data Sheet: Product Preview
Document Number: MPC5553 Rev. 2, 03/2007
MPC5553 Microcontroller Data Sheet
by: Microcontroller Division
This document provides electrical specifications, pin assignments, and package diagrams for the MPC5553 microcontroller device. For functional characteristics, refer to the MPC5553/MPC5554 Microcontroller Reference Manual.
Contents
1 2 3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.2 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . 6 3.3 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4 Electromagnetic Interference Characteristics . . . . . 9 3.5 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6 VRC/POR Electrical Specifications . . . . . . . . . . . . 10 3.7 Power-Up/Down Sequencing . . . . . . . . . . . . . . . . 11 3.8 DC Electrical Specifications. . . . . . . . . . . . . . . . . . 13 3.9 Oscillator and FMPLL Electrical Characteristics . . 20 3.10 eQADC Electrical Characteristics . . . . . . . . . . . . . 22 3.11 H7Fa Flash Memory Electrical Characteristics . . . 23 3.12 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.13 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.14 Fast Ethernet AC Timing Specifications . . . . . . . . 46 Mechanicals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.1 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.2 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . 56
1
Overview
The MPC5553 microcontroller (MCU) is a member of the MPC5500 family of microcontrollers built on the Power ArchitectureTM embedded technology. This family of parts contains many new features coupled with high performance CMOS technology to provide substantial reduction of cost per feature and significant performance improvement over the MPC500 family. The host processor core of this device complies with the Power Architecture embedded category that is 100% user-mode compatible (with floating point library) with the original Power PCTM user instruction set architecture (UISA). The embedded architecture has enhancements that improve the performance in embedded applications. This core also has additional instructions, including digital signal processing (DSP) instructions, beyond the original Power PC instruction set. This family of parts
4
(c) Freescale Semiconductor, Inc., 2007. All rights reserved.
Overview
contains many new features coupled with high performance CMOS technology to provide significant performance improvement over the MPC565. The MPC5553 of the MPC5500 family has two levels of memory hierarchy. The fastest accesses are to the 8-kilobyte unified cache. The next level in the hierarchy contains the 64-kilobyte on-chip internal SRAM and 1.5 Mbyte internal Flash memory. The internal SRAM and flash memory can hold instructions and data. The external bus interface has been designed to support most of the standard memories used with the MPC5xx family. The complex input/output timer functions of the MPC5500 family are performed by an enhanced time processor unit engine (eTPU). The eTPU engine controls 32 hardware channels. The eTPU has been enhanced over the TPU by providing 24-bit timers, double-action hardware channels, variable number of parameters per channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU can be programmed using a high-level programming language. The less complex timer functions of the MPC5500 family are performed by the enhanced modular input/output system (eMIOS). The eMIOS' 24 hardware channels are capable of single-action, double-action, pulse-width modulation (PWM), and modulus-counter operations. Motor control capabilities include edge-aligned and center-aligned PWM. Off-chip communication is performed by a suite of serial protocols including controller area networks (FlexCANs), enhanced deserial/serial peripheral interfaces (DSPI), and enhanced serial communications interfaces (eSCIs). The DSPIs support pin reduction through hardware serialization and deserialization of timer channels and general-purpose input/output (GPIO) signals. The MCU of the MPC5553 has an on-chip 40-channel enhanced queued dual analog-to-digital converter (eQADC). The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset control are also determined by the SIU. The internal multiplexer submodule (SIU_DISR) provides multiplexing of eQADC trigger sources, daisy chaining the DSPIs, and external interrupt signal multiplexing. The Fast Ethernet (FEC) module is a RISC-based controller that supports both 10 and 100 Mbps Ethernet/IEEE(R) 802.3 networks and is compatible with three different standard MAC (media access controller) PHY (physical) interfaces to connect to an external Ethernet bus. The FEC supports the 10 or 100 Mbps MII (media independent interface), and the 10 Mbps-only with a seven-wire interface, which uses a subset of the MII signals. The upper 16-bits of the 32-bit external bus interface (EBI) are used to connect to an external Ethernet device. The FEC contains built-in transmit and receive message FIFOs and DMA support.
MPC5553 Microcontroller Data Sheet, Rev. 2.0 2 Freescale Semiconductor
Ordering Information
2
Ordering Information
M PC 5553 M ZP 80 R2
Qualification status Core code Device number Temperature range Package identifier Operating frequency (MHz) Tape and reel status
Temperature Range M = -40 C to 125 C
Package Identifier ZP = 416PBGA SnPb VR = 416PBGA Pb-free VF = 208MAPBGA SnPb VM = 208MAPBGA Pb-free ZQ = 324PBGA SnPb VZ = 324PBGA Pb-free
Operating Frequency 80 = 80 MHz 112 = 112 MHz 132 = 132 MHz
Tape and Reel Status R2 = Tape and seel (blank) = Trays
Note: Not all options are available on all devices. Refer to Table 1.
Qualification Status P = Pre qualification M = Full spec qualified
Figure 1. MPC5500 Family Part Number Example Table 1. Orderable Part Numbers
Speed (MHz) Freescale Part Number1 Package Description Nominal MPC5553MVR132 MPC5553MVR112 MPC5553MVR80 MPC5553MVZ132 MPC5553MVZ112 MPC5553MVZ80 MPC5553MVM132 MPC5553MVM112 MPC5553MVM80 MPC5553MZP132 MPC5553MZP112 MPC5553MZP80 MPC5553MZQ132 MPC5553MZQ112 MPC5553MZQ80 MPC5553 Lead 324 package MPC5553 Lead 416 package MPC5553 Lead-free 208 package MPC5553 Lead-free 324 package MPC5553 Lead-free 416 package 132 112 80 132 112 80 132 112 80 132 112 80 132 112 80 Max3 (fMAX) 132 114 82 132 114 82 132 114 82 132 114 82 132 114 82 -40 C 125 C -40 C 125 C -40 C 125 C -40 C 125 C -40 C 125 C Min (TL) Max (TH) Operating Temperature2
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 3
Electrical Characteristics
Table 1. Orderable Part Numbers (continued)
Speed (MHz) Freescale Part Number1 Package Description Nominal MPC5553MVF132 MPC5553MVF112 MPC5553MVF80
1
Operating Temperature2 Min (TL) Max (TH)
Max3 (fMAX) 132 114 82
132 MPC5553 Lead 208 package 112 80
-40 C
125 C
All devices are PPC5553, rather than MPC5553, until the product qualifications. Not all configurations are available in the PPC parts. 2 The lowest operating temperature is referenced by TL; the highest operating temperature is referenced by TH. 3 Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including any frequency modulation. 80 MHz parts allow for 80 MHz + 2% modulation. However, 132 MHz devices allow 128 MHz plus two percent frequency modulation only.
3
Electrical Characteristics
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MCU.
3.1
Maximum Ratings
Table 2. Absolute Maximum Ratings1
Spec 1 2 3 4 5 6 7 8 9 10 11 12
Characteristic 1.5 V core supply voltage
3
Symbol VDD VPP VDDF VFLASH VSTBY VDDSYN VDD33 VRC33 VDDA VDDE
4
Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -1.06 -1.06 -0.3 -0.1 -VDDA -0.3
Max2 1.7 6.5 1.7 4.6 1.7 4.6 4.6 4.6 5.5 4.6 6.5 6.57 4.68 5.5 0.1 VDD 5.5
Unit V V V V V V V V V V V V V V V V
Flash program/erase voltage Flash core voltage Flash read voltage SRAM standby voltage Clock synthesizer voltage 3.3 V I/O buffer voltage Voltage regulator control input voltage Analog supply voltage (reference to VSSA) I/O supply voltage (fast I/O pads) voltage5
4
I/O supply voltage (slow and medium I/O pads) DC input VDDEH powered I/O pads VDDE powered I/O pads
VDDEH VIN
13 14 15 16
Analog reference high voltage (reference to VRL) VSS differential voltage VDD differential voltage VREF differential voltage
VRH VSS - VSSA VDD - VDDA VRH - VRL
MPC5553 Microcontroller Data Sheet, Rev. 2.0 4 Freescale Semiconductor
Electrical Characteristics
Table 2. Absolute Maximum Ratings1 (continued)
Spec 17 18 19 20 21 22 23 24 25 26 27 28 29
1
Characteristic VRH to VDDA differential voltage VRL to VSSA differential voltage VDDEH to VDDA differential voltage VDDF to VDD differential voltage This spec has been moved to Table 9, spec 43a. VSSSYN to VSS differential voltage VRCVSS to VSS differential voltage Maximum DC digital input current (per pin, applies to all digital pins)5
9
Symbol VRH - VDDA VRL - VSSA VDDEH - VDDA VDDF - VDD VSSSYN - VSS VRCVSS - VSS IMAXD IMAXA TJ TSTG TSDR MSL
Min -5.5 -0.3 -VDDA -0.3
Max2 5.5 0.3 VDDEH 0.3
Unit V V V V
-0.1 -0.1 -2 -3 TL -55.0 -- --
0.1 0.1 2 3 150.0 150.0 260.0 3
V V mA mA
oC oC oC
Maximum DC analog input current 10 (per pin, applies to all analog pins) Maximum operating temperature range 11 Die junction temperature Storage temperature range Maximum solder temperature 12 Moisture sensitivity level 13
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima can affect device reliability or cause permanent damage to the device. 2 Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress have not yet been determined. 3 1.5 V +/- 10% for proper operation. This parameter is specified at a maximum junction temperature of 150 oC. 4 All functional non-supply I/O pins are clamped to V SS and VDDE, or VDDEH. 5 AC signal overshoot and undershoot of up to +/- 2.0 V of the input voltages is permitted for an accumulative duration of 60 hours over the complete lifetime of the device (injection current not limited for this duration). 6 Internal structures hold the voltage greater than -1.0 V if the injection current limit of 2 mA is met. Keep the negative DC current greater than -0.6 V on eTPUB[15] and SINB during the internal power-on reset (POR) state. 7 Internal structures hold the input voltage less than the maximum voltage on all pads powered by V DDEH supplies, if the maximum injection current specification is met (2 mA for all pins) and VDDEH is within the operating voltage specifications. 8 Internal structures hold the input voltage less than the maximum voltage on all pads powered by V DDE supplies, if the maximum injection current specification is met (2 mA for all pins) and VDDE is within the operating voltage specifications. 9 Total injection current for all pins (including both digital and analog) must not exceed 25 mA. 10 Total injection current for all analog input pins must not exceed 15 mA. 11 Lifetime operation at these specification limits is not guaranteed. 12 Solder profile per CDF-AEC-Q100. 13 Moisture sensitivity per JEDEC test method A112.
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 5
Electrical Characteristics
3.2
Thermal Characteristics
Table 3. Thermal Characteristics
Package
The shaded rows in the following table indicate information specific to a four-layer device.
Spec
MPC5553 Thermal Characteristic
Symbol
208 MAPBGA 41 25 33 22 15 7 2
324 PBGA 30 21 24 17 12 8 2
416 PBGA 29 21 23 18 13 9 2
Unit
1 2 3 4 5 6 7
1
Junction to ambient 1, 2, natural convection (one-layer board) Junction to ambient , natural convection (four-layer board 2s2p) Junction to ambient (@200 ft./min., one-layer board) Junction to ambient (@200 ft./min., four-layer board 2s2p) Junction to board Junction to case
4 1, 3
RJA RJA RJMA RJMA RJB RJC JT
C/W C/W C/W C/W C/W C/W C/W
(four-layer board 2s2p)
6,
5
Junction to package top
natural convection
2 3 4 5 6
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.
3.2.1
General Notes for Specifications at Maximum Junction Temperature
An estimation of the device junction temperature, TJ, can be obtained from the equation: TJ = TA + (RJA x PD) where: TA = ambient temperature for the package (oC) RJA = junction to ambient thermal resistance (oC/W) PD = power dissipation in the package (W) The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance depends on the:
MPC5553 Microcontroller Data Sheet, Rev. 2.0 6 Freescale Semiconductor
Electrical Characteristics
* * * *
Construction of the application board (number of planes) Effective size of the board which cools the component Quality of the thermal and electrical connections to the planes Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced. As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. The value obtained on a board with the internal planes is usually within the normal range if the application board has: * One oz (35 micron nominal thickness) internal planes * Components are well separated * Overall power dissipation on the board is less than 0.02 W/cm2 The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: TJ = TB + (RJB x PD) where: TJ = junction temperature (oC) TB = board temperature at the package perimeter (oC/W) RJB = junction-to-board thermal resistance (oC/W) per JESD51-8 PD = power dissipation in the package (W) When the heat loss from the package case to the air does not factor into the calculation, an acceptable value for the junction temperature is predictable. Ensure the application board is similar to the thermal test condition, with the component soldered to a board with internal planes. The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal resistance: RJA = RJC + RCA where: RJA = junction-to-ambient thermal resistance (oC/W) RJC = junction-to-case thermal resistance (oC/W) RCA = case-to-ambient thermal resistance (oC/W)
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 7
Electrical Characteristics
RJC is device related and is not affected by other factors. The thermal environment can be controlled to change the case-to-ambient thermal resistance, RCA. For example, change the air flow around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to the heat sink to ambient. For most packages, a better model is required. A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple estimations and for computational fluid dynamics (CFD) thermal models. To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization parameter (JT) to determine the junction temperature by measuring the temperature at the top center of the package case using the following equation: TJ = TT + (JT x PD) where: TT = thermocouple temperature on top of the package (oC) JT = thermal characterization parameter (oC/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests on the package. A small amount of epoxy is placed on the thermocouple junction and approximately 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire. References: Semiconductor Equipment and Materials International 805 East Middlefield Rd. Mountain View, CA., 94043 (415) 964-5111 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the web at http://www.jedec.org. * 1. C.E. Triplett and B. Joiner, "An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module," Proceedings of SemiTherm, San Diego, 1998, pp. 47-54. * 2. G. Kromann, S. Shidore, and S. Addison, "Thermal Modeling of a PBGA for Air-Cooled Applications," Electronic Packaging and Production, pp. 53-58, March 1998. * 3. B. Joiner and V. Adams, "Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling," Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.
MPC5553 Microcontroller Data Sheet, Rev. 2.0 8 Freescale Semiconductor
Electrical Characteristics
3.3
Package
The MPC5553 is available in packaged form. Package options are listed in Section 2, "Ordering Information." Refer to Section 4, "Mechanicals," for pinouts and package drawings.
3.4
Spec 1 2 3 4 5 6 7
1
EMI (Electromagnetic Interference) Characteristics
Table 4. EMI Testing Specifications1
Characteristic Scan range Operating frequency VDD operating voltages VDDSYN, VRC33, VDD33, VFLASH, VDDE operating voltages VPP, VDDEH, VDDA operating voltages Maximum amplitude Operating temperature Minimum 0.15 -- -- -- -- -- -- Typical -- -- 1.5 3.3 5.0 -- -- Maximum 1000 132 -- -- -- 142 323 25
oC
Unit MHz MHz V V V dBuV
EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03. Qualification testing was performed on the MPC5554 and applied to the MPC5500 family as generic EMI performance data. 2 Measured with single-chip EMI program. 3 Measured with expanded EMI program.
3.5
ESD Characteristics
Table 5. ESD Ratings1, 2
Characteristic Symbol Value 2000 R1 C 1500 100 500 (all pins) 750 (corner pins) -- -- -- 1 1 1 V Unit V pF
ESD for Human Body Model (HBM) HBM circuit description
ESD for Field Induced Charge Model (FDCM) Number of pulses per pin: Positive pulses (HBM) Negative pulses (HBM) Interval of pulses
1 2
-- -- second
All ESD testing conforms to CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. Device failure is defined as: if after exposure to ESD pulses, the device no longer meets the device specification requirements. Complete DC parametric and functional testing will be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 9
Electrical Characteristics
3.6
Voltage Regulator Controller (VRC) and Power-On Reset (POR) Electrical Specifications
Table 6. VRC/POR Electrical Specifications
Spec 1 2 3 4 5 6 7
Characteristic 1.5 V (VDD) POR negated (ramp up) 1.5 V (VDD) POR asserted (ramp down) 3.3 V (VDDSYN) POR negated (ramp up) 3.3 V (VDDSYN) POR asserted (ramp down) RESET pin supply (VDDEH6) POR negated (ramp up)1 RESET pin supply (VDDEH6) POR asserted (ramp down)1 VRC33 voltage before the regulator controller allows the pass transistor to start turning on VRC33 voltage when the regulator controller allows the pass transistor to completely turn on2, 3 VRC33 voltage greater than the voltage at which the VRC keeps the 1.5 V supply in regulation4, 5 Current can be sourced by VRCCTL - 40o C 25o C 150o C (Tj)
Symbol V_POR15 V_POR33 V_POR5 V_TRANS_START V_TRANS_ON V_VRC33REG I_VRCCTL6
Min 1.1 1.1 2.0 2.0 2.0 2.0 1.0 2.0 3.0
Max 1.35 1.35 2.85 2.85 2.85 2.85 2.0 2.85 --
Units V V V V V V mA
11.0 9.0 7.5 VDD33_LAG --
-- -- -- 1.0
mA mA mA V
8
Voltage differential during power up such that: VDD33 can lag VDDSYN or VDDEH6, before VDDSYN and VDDEH6 reach the V_POR33 and V_POR5 minimums respectively. Absolute value of slew rate on power supply pins Required gain: IDD / I_VRCCTL (@VDD = 1.35 V, fsys = fMAX)5, 7 - 40o C 25o C 150o C (Tj)
9 10
-- BETA8 55.09 58.09 70.0
9
50
V/ms
-- -- 500
-- -- --
1 2 3 4 5
6 7 8
VIL_S (Table 9, Spec15) is guaranteed to scale with VDDEH6 down to V_POR5. Supply full operating current for the 1.5 V supply when the 3.3 V supply reaches this range. It is possible to reach the current limit during ramp up--do not treat this event as short circuit current. At peak current for device. Requires compliance with Freescale's recommended board requirements and transistor recommendations. Board signal traces/routing from the VRCCTL package signal to the base of the external pass transistor and between the emitter of the pass transistor to the VDD package signals must have a maximum of 100 nH inductance and minimal resistance (less than 1 ). VRCCTL must have a nominal 1 F phase compensation capacitor to ground. VDD must have a 20 F (nominal) bulk capacitor (greater than 4 F over all conditions, including lifetime). Place high-frequency bypass capacitors consisting of eight 0.01 F, two 0.1 F, and one 1 F capacitors around the package on the VDD supply signals. I_VRCCTL is measured at the following conditions: VDD = 1.35 V, VRC33 = 3.1 V, V_VRCCTL = 2.2 V. Values are based on IDD from high-use applications as explained in the IDD Electrical Specification. BETA is measured on a per-part basis and is calculated as (IDD / I_VRCCTL), and represents the worst-case external transistor BETA.
MPC5553 Microcontroller Data Sheet, Rev. 2.0 10 Freescale Semiconductor
Electrical Characteristics
9
Preliminary value. Final specification pending characterization.
3.7
Power-Up/Down Sequencing
Power sequencing between the 1.5 V power supply and VDDSYN or the RESET power supplies is required if using an external 1.5 V power supply with VRC33 tied to ground (GND). To avoid power-sequencing, VRC33 must be powered up within the specified operating range, even if the on-chip voltage regulator controller is nit used. Refer to Section 3.7.2, "Power-Up Sequence (VRC33 Grounded)," and Section 3.7.3, "Power-Down Sequence (VRC33 Grounded)." Power sequencing requires that VDD33 must reach a certain voltage where the values are read as ones before the POR signal negates. Refer to Section 3.7.1, "Input Value of Pins During POR Dependent on VDD33." Although power sequencing is not required between VRC33 and VDDSYN during power up, VRC33 must not lead VDDSYN by more than 600 mV or lag by more than 100 mV for the VRC stage turn-on to operate within specification. Higher spikes in the emitter current of the pass transistor occur if VRC33 leads or lags VDDSYN by more than these amounts. The value of that higher spike in current depends on the board power supply circuitry and the amount of board level capacitance. Furthermore, when all of the PORs negate, the system clock starts to toggle, adding another large increase of the current consumed by VRC33. If VRC33 lags VDDSYN by more than 100 mV, the increase in current consumed can drop VDD low enough to assert the 1.5 V POR again. Oscillations are possible when the 1.5 V POR asserts and stops the system clock, causing the voltage on VDD to rise until the 1.5 V POR negates again. All oscillations stop when VRC33 is powered sufficiently. When powering down, VRC33 and VDDSYN have no delta requirement to each other, because the bypass capacitors internal and external to the device are already charged. When not powering up or down, no delta between VRC33 and VDDSYN is required for the VRC to operate within specification. There are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current spikes, and so on. Therefore, the state of the I/O pins during power up/down varies depending on which supplies are powered. Table 7 gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type).
Table 7. Power Sequence Pin Status for Fast Pads
Pin Status for Fast Pad Output Driver VDDE Low VDDE VDDE VDDE VDDE VDDE VDD33 -- Low Low VDD33 VDD33 VDD33 VDD -- Low VDD Low VDD VDD POR Asserted Asserted Asserted Asserted Asserted Negated pad_fc (fast) Low High High High impedance (Hi-Z) Hi-Z Functional
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 11
Electrical Characteristics
Table 8 gives the pin state for the sequence cases for all pins with pad type pad_mh (medium type) and pad_sh (slow type).
Table 8. Power Sequence Pin Status for Medium / Slow Pads
Pin Status for Medium and Slow Pad Output Driver VDDEH Low VDDEH VDDEH VDDEH VDD -- Low VDD VDD POR Asserted Asserted Asserted Negated pad_mh (medium) pad_sh (slow) Low High impedance (Hi-Z) Hi-Z Functional
3.7.1
Input Value of Pins During POR Dependent on VDD33
When powering up the device, VDD33 must not lag the latest VDDSYN or RESET power pin (VDDEH6) by more than the VDD33 lag specification listed in Table 6, spec 8. This avoids accidentally selecting the bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and therefore cannot read the default state when POR negates. VDD33 can lag VDDSYN or the RESET power pin (VDDEH6), but cannot lag both by more than the VDD33 lag specification. This VDD33 lag specification applies during power up only. VDD33 has no lead or lag requirements when powering down.
3.7.2
Power-Up Sequence (VRC33 Grounded)
The 1.5 V VDD power supply must rise to 1.35 V before the 3.3 V VDDSYN power supply and the RESET power supply rises above 2.0 V. This ensures that digital logic in the PLL for the 1.5 V power supply does not begin to operate below the specified operation range lower limit of 1.35 V. Because the internal 1.5 V POR is disabled, the internal 3.3 V POR or the RESET power POR must hold the device in reset. Since they can negate as low as 2.0 V, VDD must be within specification before the 3.3 V POR and the RESET POR negate.
VDDSYN and RESET Power
VDD 2.0 V 1.35 V
VDD must reach 1.35 V before VDDSYN and the RESET power reach 2.0 V
Figure 2. Power-Up Sequence (VRC33 Grounded)
MPC5553 Microcontroller Data Sheet, Rev. 2.0 12 Freescale Semiconductor
Electrical Characteristics
3.7.3
Power-Down Sequence (VRC33 Grounded)
The only requirement for the power-down sequence when VRC33 is grounded is that if VDD decreases to less than its operating range, VDDSYN or the RESET power must decrease to less than 2.0 V before the VDD power is allowed to increase to its operating range. This ensures that the digital 1.5 V logic, which is reset by the ORed POR only and can cause the 1.5 V supply to decrease below its specification, is reset properly.
3.8
DC Electrical Specifications
Table 9. DC Electrical Specifications
Spec 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Characteristic Core supply voltage (average DC RMS voltage) I/O supply voltage (fast I/O) I/O supply voltage (slow / medium I/O) 3.3 V I/O buffer voltage Voltage regulator control input voltage Analog supply voltage1
Symbol VDD VDDE VDDEH VDD33 VRC33 VDDA VPP VFLASH VSTBY VDDSYN VIH_F VIL_F VIH_S VIL_S VHYS_F VHYS_S VINDC VOH_F VOH_S VOL_F VOL_S
Min 1.35 1.62 3.0 3.0 3.0 4.5 4.5 3.0 0.8 3.0 0.65 x VDDE VSS - 0.3
Max 1.65 3.6 5.25 3.6 3.6 5.25 5.25 3.6 1.2 3.6 VDDE + 0.3 0.35 x VDDE
Unit V V V V V V V V V V V V V V V V V V V V V pF pF pF pF
Flash programming voltage2 Flash read voltage SRAM standby voltage3 Clock synthesizer operating voltage Fast I/O input high voltage Fast I/O input low voltage Medium / slow I/O input high voltage Medium / slow I/O input low voltage Fast I/O input hysteresis Medium / slow I/O input hysteresis Analog input voltage Fast I/O output high voltage ( IOH_F = -2.0 mA ) Slow / medium I/O output high voltage ( IOH_S = -2.0 mA ) Fast I/O output low voltage ( IOL_F = 2.0 mA ) Slow / medium I/O output low voltage ( IOL_S = 2.0 mA ) Load capacitance (fast I/O) DSC (SIU_PCR[8:9] ) = 0b00 DSC (SIU_PCR[8:9] ) = 0b01 DSC (SIU_PCR[8:9] ) = 0b10 DSC (SIU_PCR[8:9] ) = 0b11
4
0.65 x VDDEH VDDEH + 0.3 VSS - 0.3 0.35 x VDDEH
0.1 x VDDE 0.1 x VDDEH VSSA - 0.3 0.8 x VDDE 0.8 x VDDEH -- -- -- -- -- -- VDDA + 0.3 -- -- 0.2 x VDDE 0.2 x VDDEH 10 20 30 50
CL
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 13
Electrical Characteristics
Table 9. DC Electrical Specifications (continued)
Spec 24 25 26 Characteristic Input capacitance (digital pins) Input capacitance (analog pins) Input capacitance (Shared digital and analog pins AN[12]_MA[0]_SDS, AN[12]_MA[1]_SDO, AN[14]_MA[2]_SDI, and AN[15]_FCK) Symbol CIN CIN_A CIN_M Min -- -- -- Max 7 10 12 Unit pF pF pF
27a Operating current5 1.5 V supplies @ 132 MHz: VDD (including VDDF max current)6, 7 @1.65 V typical use VDD (including VDDF max current)6, 7 @1.35 V typical use VDD (including VDDF max current) 7, 8 @1.65 V high use VDD (including VDDF max current)7, 8@1.35 V high use 27b Operating current 51.5 V supplies @ 114 MHz: VDD (including VDDF max current)6, 7@1.65 V typical use VDD (including VDDF max current)6, 7@1.35 V typical use VDD (including VDDF max current)7, 8 @1.65 V high use VDD (including VDDF max current)7, 8 @1.35 V high use 27c Operating current5 1.5 V supplies @ 82 MHz: VDD (including VDDF max current)6, 7 @1.65 V typical use VDD (including VDDF max current)6, 7 @1.35 V typical use VDD (including VDDF max current)7, 8 @1.65 V high use VDD (including VDDF max current)7, 8 @1.35 V high use 27d Refer to Figure 3 for an interpolation of this data. 10 IDDSTBY @ 25o C VSTBY @ 0.8 V VSTBY @ 1.0 V VSTBY @ 1.2 V IDDSTBY @ 60o C VSTBY @ 0.8 V VSTBY @ 1.0 V VSTBY @ 1.2 V IDDSTBY @ 150o C (Tj) VSTBY @ 0.8 V VSTBY @ 1.0 V VSTBY @ 1.2 V 28 Operating current 3.3 V supplies @ 132 MHz VDD3311 IDD33 -- 2 + (values derived from procedure of Footnote 11) 10 15 mA IDD IDD IDD IDD -- -- -- -- 3509 2909 4009 3309 mA mA mA mA IDD IDD IDD IDD -- -- -- -- 4609 3809 5209 4209 mA mA mA mA IDD IDD IDD IDD -- -- -- -- 5509 4509 6009 4909 mA mA mA mA
IDDSTBY IDDSTBY IDDSTBY
-- -- --
20 30 50
A A A A A A A A A
IDDSTBY IDDSTBY IDDSTBY
-- -- --
70 100 200
IDDSTBY IDDSTBY IDDSTBY
-- -- --
1200 1500 2000
VFLASH VDDSYN
IVFLASH IDDSYN
-- --
mA mA
MPC5553 Microcontroller Data Sheet, Rev. 2.0 14 Freescale Semiconductor
Electrical Characteristics
Table 9. DC Electrical Specifications (continued)
Spec 29 Characteristic Operating current 5.0 V supplies (12 MHz ADCLK): VDDA (VDDA0 + VDDA1) Analog reference supply current (VRH, VRL) VPP 30 Operating current VDDE12 supplies: VDDEH1 VDDE2 VDDE3 VDDEH4 VDDE5 VDDEH6 VDDE7 VDDEH8 VDDEH9 Fast I/O weak pullup current13 1.62-1.98 V 2.25-2.75 V 3.00-3.60 V Fast I/O weak pulldown current13 1.62-1.98 V 2.25-2.75 V 3.00-3.60 V 32 Slow / medium I/O weak pullup/down current14 3.0-3.6 V 4.5-5.5 V I/O input leakage current15 DC injection current (per pin) Analog input current, channel off 16 IACT_F 10 20 20 IACT_S IINACT_D IIC IINACT_A IINACT_AD VSS - VSSA VRL VRL - VSSA VRH VRH - VRL VSSSYN - VSS VRCVSS - VSS VDDF - VDD VRC33 - VDDSYN 10 20 - 2.5 - 2.0 -150 - 2.5 - 100 VSSA - 0.1 -100 VDDA - 0.1 4.5 -50 -50 -100 -0.1 100 130 170 150 170 2.5 2.0 150 2.5 100 VSSA + 0.1 100 VDDA + 0.1 5.25 50 50 100 0.1
18
Symbol
Min
Max
Unit
IDDA IREF IPP IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 IDD7 IDD8 IDD9
-- -- -- -- -- -- -- -- -- -- -- -- 10 20 20
20.0 1.0 25.0 Refer to Footnote 12
mA mA mA mA mA mA mA mA mA mA mA mA A A A A A A A A A mA nA A mV V mV V V mV mV mV V
31
110 130 170
33 34 35
35a Analog input current, shared analog / digital pins (AN[12], AN[13], AN[14], AN[15]) 36 37 38 39 40 41 42 43 VSS differential voltage17 Analog reference low voltage VRL differential voltage Analog reference high voltage VREF differential voltage VSSSYN to VSS differential voltage VRCVSS to VSS differential voltage VDDF to VDD differential voltage2
43a VRC33 to VDDSYN differential voltage
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 15
Electrical Characteristics
Table 9. DC Electrical Specifications (continued)
Spec 44 45 46
1 2
Characteristic Analog input differential signal range (with common mode 2.5 V) Operating temperature range, ambient (packaged) Slew rate on power-supply pins
Symbol VIDIFF TA = (TL to TH) --
Min - 2.5 TL --
Max 2.5 TH 50
Unit V
C
V/ms
| VDDA0 - VDDA1 | must be < 0.1 V. VPP can drop to 3.0 V during read operations. 3 During standby operation, if standby operation is not required, connect VSTBY to ground. 4 Applies to CLKOUT, external bus pins, and Nexus pins. 5 Maximum average RMS DC current. 6 Average current measured on Automotive benchmark. 7 Peak currents can be higher on specialized code. 8 High use current measured while running optimized SPE assembly code with all code and data 100% locked in cache (0% miss rate) with all channels of the eMIOS and eTPU running autonomously, plus the eDMA transferring data continuously from SRAM to SRAM. Higher currents are possible if an idle loop that crosses cache lines is run from cache. Design and write code to avoid this condition. 9 Preliminary. Final specification pending characterization. 10 Figure 3 shows an illustration of the IDD STBY values interpolated for these temperature values. 11 Power requirements for the V supply depend on the frequency of operation and load of all I/O pins, and the voltages on DD33 the I/O segments. Refer to Table 11 for values to calculate power dissipation for specific operation. 12 Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a particular I/O segment, and the voltage of the I/O segment. Refer to Table 10 for values to calculate power dissipation for specific operation. The total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment. 13 Absolute value of current, measured at V and V . IL IH 14 Absolute value of current, measured at V and V . IL IH 15 Weak pullup/down inactive. Measured at V = 3.6 V and VDDEH = 5.25 V. Applies to pad types: pad_fc, pad_sh, and pad_mh. DDE 16 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8 oC to 12 oC, in the ambient temperature range of 50 oC to 125 oC. Applies to pad types: pad_a and pad_ae. 17 V SSA refers to both VSSA0 and VSSA1. | VSSA0 - VSSA1 | must be < 0.1 V. 18 Up to 0.6 V during power up and power down.
MPC5553 Microcontroller Data Sheet, Rev. 2.0 16 Freescale Semiconductor
Electrical Characteristics
Figure 3 shows an approximate interpolation of the ISTBY worst-case specification to help estimate the values at different voltages and temperatures. The vertical lines inside the graph show the actual specifications listed in Table 9. Refer to the IDDSTBY specifications (27d) in Table 9 for more information.
ISTBY Related to Junction Temperature
2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 0.8V 1.0V 1.2V
A
Temperature (C)
Figure 3. ISTBY Worst-case Specifications
3.8.1
I/O Pad Current Specifications
The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption is the sum of all output pin currents for a particular segment. The output pin current can be calculated from Table 10 based on the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 10.
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 17
Electrical Characteristics
Table 10. I/O Pad Average DC Current1
Spec 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1 2
Pad Type
Symbol
Frequency (MHz) 25
Load2 (pF) 50 50 50 200 50 50 50 200 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50
Voltage (V) 5.25 5.25 5.25 5.25 5.25 5.25 5.25 5.25 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98
Drive Select / Slew Rate Control Setting 11 01 00 00 11 01 00 00 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11
Current (mA) 8.0 3.2 0.7 2.4 17.3 6.5 1.1 3.9 2.8 5.2 8.5 11.0 1.6 2.9 4.2 6.7 2.4 4.4 7.2 9.3 1.3 2.5 3.5 5.7 1.7 3.1 5.1 6.6 1.0 1.8 2.5 4.0
Slow
IDRV_SH
10 2 2 50 20 3.33 3.33 66 66 66 66 66 66 66 66 56 56 56 56 56 56 56 56 40 40 40 40 40 40 40 40
Medium
IDRV_MH
Fast
IDRV_FC
These values are estimates from simulation and are not tested. Currents apply to output pins only. All loads are lumped.
MPC5553 Microcontroller Data Sheet, Rev. 2.0 18 Freescale Semiconductor
Electrical Characteristics
3.8.2
I/O Pad VDD33 Current Specifications
The power consumption of the VDD33 supply dependents on the usage of the pins on all I/O segments. The power consumption is the sum of all input and output pin VDD33 currents for all I/O segments. The output pin VDD33 current can be calculated from Table 11 based on the voltage, frequency, and load on all fast (pad_fc) pins. The input pin VDD33 current can be calculated from Table 11 based on the voltage, frequency, and load on all pad_sh and pad_sh pins. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 11.
Table 11. VDD33 Pad Average DC Current1
Spec Pad Type Symbol Frequency (MHz) Load2 (pF) Inputs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
1
VDD33 (V)
VDDE (V)
Drive Select
Current (mA)
Slow Medium
I33_SH I33_MH
66 66 66 66 66 66 66 66 66 66 56 56 56 56 56 56 56 56 40 40 40 40 40 40 40 40
0.5 0.5 Outputs 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50
3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6
5.5 5.5 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98
NA NA 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11
0.003 0.003 0.35 0.53 0.62 0.79 0.35 0.44 0.53 0.7 0.30 0.45 0.52 0.67 0.30 0.37 0.45 0.60 0.21 0.31 0.37 0.48 0.21 0.27 0.32 0.42
Fast
I33_FC
These values are estimated from simulation and not tested. Currents apply to output pins for the fast pads only and to input pins for the slow and medium pads only. 2 All loads are lumped.
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 19
Electrical Characteristics
3.9
Oscillator and FMPLL Electrical Characteristics
Table 12. FMPLL Electrical Specifications
(VDDSYN = 3.0-3.6 V; VSS = VSSSYN = 0.0 V; TA = TL to TH)
Spec
Characteristic PLL reference frequency range: Crystal reference External reference Dual controller (1:1 mode) System frequency 1 System clock period Loss of reference frequency 3 Self clocked mode (SCM) frequency 4 EXTAL input high voltage crystal mode 5
Symbol
Minimum
Maximum
Unit MHz
1
fref_crystal fref_ext fref_1:1 fsys tCYC fLOR fSCM VIHEXT
8 8 24 fICO(MIN) / 2RFD -- 100 7.4 VXTAL + 0.4 V [(VDDE5 / 2) + 0.4 V]
20 20 fsys / 2 fMAX 2 1 / fsys 1000 17.5 MHz ns kHz MHz
2 3 4 5
-- --
V V
6 All other modes (dual controller (1:1), bypass, external reference) EXTAL input low voltage crystal mode 6 7 All other modes (dual controller (1:1), bypass, external reference) 8 9 10 11 XTAL current 7 Total on-chip stray capacitance on XTAL Total on-chip stray capacitance on EXTAL Crystal manufacturer's recommended capacitive load Discrete load capacitance to connect to EXTAL Discrete load capacitance to connect to XTAL PLL lock time9 Dual controller (1:1) clock skew (between CLKOUT and EXTAL) 10, 11 Duty cycle of reference Frequency un-LOCK range Frequency LOCK range VILEXT IXTAL CS_XTAL CS_EXTAL CL CL_EXTAL CL_XTAL tlpll tskew tDC fUL fLCK -- [(VDDE5 / 2) - 0.4 V] 3 1.5 1.5 Refer to crystal specification (2 x CL) - CS_EXTAL - CPCB_EXTAL8 (2 x CL) - CS_XTAL - CPCB_XTAL8 750 2 V VIHEXT
VILEXT
--
VXTAL - 0.4 V
V
0.8 -- -- Refer to crystal specification --
mA pF pF pF
12
pF
13 14 15 16 17 18
--
pF s ns
-- -2
40 - 4.0 - 2.0
60 4.0 2.0
% % fSYS % fSYS
MPC5553 Microcontroller Data Sheet, Rev. 2.0 20 Freescale Semiconductor
Electrical Characteristics
Table 12. FMPLL Electrical Specifications (continued)
(VDDSYN = 3.0-3.6 V; VSS = VSSSYN = 0.0 V; TA = TL to TH) Spec Characteristic CLKOUT period jitter,12, 13 measured at fSYS maximum peak-to-peak jitter (clock edge to clock edge) Long term jitter (averaged over 2 ms interval) Frequency modulation range limit 14 (do not exceed fsys maximum) ICO frequency fico = [ fref x (MFD + 4) ] / (PREDIV + 1)15 Predivider output frequency (to PLL) Symbol CJITTER -- -- 5.0 0.01 % fCLKOUT Minimum Maximum Unit
19
20
CMOD fico fPREDIV
0.8
2.4
%fSYS MHz
21 22
1 2
48
fsys fMAX
4
MHz
All internal registers retain data at 0 Hz. Up to the maximum frequency rating of the device (refer to Table 1). 3 Loss of reference frequency is defined as the reference frequency detected internally, which transitions the PLL into self-clocked mode. 4 The PLL operates at self-clocked mode (SCM) frequency when the reference frequency falls below f LOR. SCM frequency is measured on the CLKOUT ball with the divider set to divide-by-two of the system clock. NOTE: In SCM, the MFD and PREDIV have no effect and the RFD is bypassed. 5 Use the EXTAL input high voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or resonators). (Vextal - Vxtal) must be 400 mV for the oscillator's comparator to produce the output clock. 6 Use the EXTAL input low voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or resonators). (Vxtal - Vextal) must be 400 mV for the oscillator's comparator to produce the output clock. 7I xtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. 8C PCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively. 9 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). From power up with crystal oscillator reference, the lock time also includes the crystal startup time. 10 PLL is operating in 1:1 PLL mode. 11 V DDE = 3.0-3.6 V 12 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f . sys Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the jitter percentage for a given interval. CLKOUT divider is set to divide-by-two. 13 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of (jitter + Cmod). 14 Modulation depth selected must not result in f sys value greater than the fsys maximum specified value. 15 f RFD). sys = fico / (2
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 21
Electrical Characteristics
3.10
Spec 1 2 3 4 5 6 7 8 9 10 11
eQADC Electrical Characteristics
Table 13. eQADC Conversion Specifications (Operating)
Characteristic ADC clock (ADCLK) frequency1 Conversion cycles Differential Single ended Stop mode recovery time2 Resolution
3
Symbol FADCLK CC
Minimum 1 13 + 2 (15) 14 + 2 (16)
Maximum 12 13 + 128 (141) 14 + 128 (142) -- -- 4 8 34 64 4
5
Unit MHz ADCLK cycles s mV Counts3 Counts Counts Counts Counts Counts mA
TSR -- INL6 INL12 DNL6 DNL12 OFFWC GAINWC IINJ EINJ
10 1.25 -4 -8 -3
4
INL: 6 MHz ADC clock INL: 12 MHz ADC clock DNL: 6 MHz ADC clock DNL: 12 MHz ADC clock Offset error with calibration Full-scale gain error with calibration Disruptive input injection current 7, 8, 9, 10
-6 4 -4 5 -8 6 -1
86 1
12
Incremental error due to injection current. All channels have same 10 k < Rs <100 k Channel under test has Rs = 10 k, IINJ = IINJMAX, IINJMIN Total Unadjusted Error for single ended conversions with calibration11, 12, 13, 14, 15
-4
4
Counts
13
1
TUE
-4
4
Counts
Conversion characteristics vary with FADCLK rate. Reduced conversion accuracy occurs at maximum FADCLK rate. The maximum value is based on 800 KS/s and the minimum value is based on 20 MHz oscillator clock frequency divided by a maximum 16 factor. 2 Stop mode recovery time begins when the ADC control register enable bits are set until the ADC is ready to perform conversions. 3 At V RH - VRL = 5.12 V, one least significant bit (LSB) = 1.25, mV = one count. 4 Guaranteed 10-bit monotonicity. 5 The absolute value of the offset error without calibration 100 counts. 6 The absolute value of the full scale gain error without calibration 120 counts. 7 Below disruptive current conditions, the channel being stressed has conversion values of: 0x3FF for analog inputs greater than VRH, and 0x000 for values less than VRL. This assumes that VRH VDDA and VRL VSSA due to the presence of the sample amplifier. Other channels are not affected by non-disruptive conditions. 8 Exceeding the limit can cause a conversion error on both stressed and unstressed channels. Transitions within the limit do not affect device reliability or cause permanent damage. 9 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values using VPOSCLAMP = VDDA + 0.5 V and VNEGCLAMP = - 0.3 V, then use the larger of the calculated values. 10 Condition applies to two adjacent pads on the internal pad. 11 The TUE specification is always less than the sum of the INL, DNL, offset, and gain errors due to canceling errors. 12 TUE does not apply to differential conversions. 13 Measured at 6 MHz ADC clock. TUE with a 12 MHz ADC clock is: -16 counts < TUE < 16 counts. 14 TUE includes all internal device errors such as internal reference variation (75% Ref, 25% Ref). 15 Depending on the input impedance, the analog input leakage current (DC Electrical specification 35a) can affect the actual TUE measured on analog channels AN[12], AN[13], AN[14], AN[15].
MPC5553 Microcontroller Data Sheet, Rev. 2.0 22 Freescale Semiconductor
Electrical Characteristics
3.11
Spec
H7Fa Flash Memory Electrical Characteristics
Table 14. Flash Program and Erase Specifications1
Flash Program Characteristic Doubleword (64 bits) program time4 Page program time
4
Spec 3 4 7 9 10 8 11
1 2 3 4 5 6
Symbol Tdwprogram Tpprogram T16kpperase T48kpperase T64kpperase T128kpperase --
Min -- -- -- -- -- -- 25
Typical 10 22 325 435 525 675 --
Initial Max2 -- 44
5
Max3 500 500 5000 5000 5000 15,000 --
Unit s s ms ms ms ms MHz
16 Kbyte block pre-program and erase time 48 Kbyte block pre-program and erase time 64 Kbyte block pre-program and erase time 128 Kbyte block pre-program and erase time Minimum operating frequency for program and erase operations6
525 525 675 1800 --
Typical program and erase times assume nominal supply values and operation at 25 oC. Initial factory condition: 100 program/erase cycles, 25 oC, typical supply voltage, 80 MHz minimum system frequency. The maximum erase time occurs after the specified number of program/erase cycles. This maximum value is characterized but not guaranteed. Actual hardware programming times. This does not include software overhead. Page size is 256 bits (8 words). Read frequency of the flash can be up to the maximum operating frequency of the device. There is no minimum read frequency condition.
Table 15. Flash EEPROM Module Life (Full Temperature Range)
Spec 1a 1b Characteristic Number of program/erase cycles per block for 16 Kbyte, 48 Kbyte, and 64 Kbyte blocks over the operating temperature range (TJ) Number of program/erase cycles per block for 128 Kbyte blocks over the operating temperature range (TJ) Data retention Blocks with 0-1,000 P/E cycles Blocks with 1,001-100,000 P/E cycles Symbol P/E P/E Retention 20 5 Min 100,000 10,000 Typical1 -- Unit cycles
100,000 cycles -- years
2
1
Typical endurance is evaluated at 25o C. Product qualification is performed to the minimum specification. For additional information on the Freescale definition of typical endurance, refer to engineering bulletin EB619 Typical Endurance for Nonvolatile Memory.
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 23
Electrical Characteristics
Table 16 shows the FLASH_BIU settings versus frequency of operation. Refer to the device reference manual for definitions of these bit fields.
Table 16. FLASH_BIU Settings vs. Frequency of Operation
Maximum Frequency (MHz) Up to and including 82 MHz1 APC 0b001 RWSC 0b001 WWSC 0b01 DPFEN 0b00, 0b01, or 0b112 0b00, 0b01, or 0b112 0b00, 0b01, or 0b112 0b00 IPFEN 0b00, 0b01, or 0b112 0b00, 0b01, or 0b112 0b00, 0b01, or 0b112 0b00 PFLIM 0b000 to 0b1103 0b000 to 0b1103 0b000 to 0b1103 0b000 BFEN 0b0, 0b14 0b0, 0b14 0b0, 0b14 0b0
Up to and including 102 MHz5
0b001
0b010
0b01
Up to and including132 MHz6
0b010
0b011
0b01
Default setting after reset
1 2 3 4 5 6
0b111
0b111
0b11
Allows for 80 MHz system clock with 2% frequency modulation. For maximum flash performance, set to 0b11. For maximum flash performance, set to 0b110. For maximum flash performance, set to 0b1. Allows for 100 MHz system clock with 2% frequency modulation. Allows for 128 MHz system clock with 2% frequency modulation.
3.12
3.12.1
AC Specifications
Pad AC Specifications
Table 17. Pad AC Specifications (VDDEH = 5.0 V, VDDE = 1.8 V)1
SRC/DSC (binary) 11 Out Delay2, 3, 4 (ns) 26 82 75 137 377 476 16 43 34 61 192 239 Rise / Fall4, 5 (ns) 15 60 40 80 200 260 8 30 15 35 100 125 Load Drive (pF) 50 200 50 200 50 200 50 200 50 200 50 200
Spec
Pad
1
Slow high voltage (SH)
01
00
11
2
Medium high voltage (MH)
01
00
MPC5553 Microcontroller Data Sheet, Rev. 2.0 24 Freescale Semiconductor
Electrical Characteristics
Table 17. Pad AC Specifications (VDDEH = 5.0 V, VDDE = 1.8 V)1 (continued)
Spec Pad SRC/DSC (binary) 00 3 Fast 01 10 11 4 5
1
Out Delay2, 3, 4 (ns)
Rise / Fall4, 5 (ns) 2.7
Load Drive (pF) 10 20 30 50 50 50
3.1
2.5 2.4 2.3
Pullup/down (3.6 V max) Pullup/down (5.5 V max)
-- --
-- --
7500 9000
2 3 4 5
These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at FSYS = 132 MHz, VDD = 1.35-1.65 V, VDDE = 1.62-1.98 V, VDDEH = 4.5-5.5 V, VDD33 and VDDSYN = 3.0-3.6 V, TA = TL to TH. This parameter is supplied for reference and is guaranteed by design and tested. Out delay is shown in Figure 4. Add a maximum of one system clock to the output delay for delay with respect to system clock. Delay and rise and fall are measured to 20% or 80% of the respective signal. This parameter is guaranteed by characterization before qualification rather than 100% tested.
Table 18. De-rated Pad AC Specifications (VDDEH = 3.3 V, VDDE = 3.3 V)1
Spec Pad SRC/DSC (binary) 11 Out Delay2, 3, 4 (ns) 39 120 101 188 507 597 23 64 50 90 261 305 Rise/Fall3, 5 (ns) 23 87 52 111 248 312 12 44 22 50 123 156 2.4 3.2 2.2 2.1 2.1 -- -- 7500 9500 Load Drive (pF) 50 200 50 200 50 200 50 200 50 200 50 200 10 20 30 50 50 50
1
Slow high voltage (SH)
01
00
11
2
Medium high voltage (MH)
01
00 00 3 Fast 01 10 11 4 5
1
Pullup/down (3.6 V max) Pullup/down (5.5 V max)
-- --
These are worst-case values that are estimated from simulation and not tested. The values in the table are simulated at: FSYS = 132 MHz; VDD = 1.35-1.65 V; VDDE = 3.0-3.6 V; VDDEH = 3.0-3.6 V; VDD33 and VDDSYN = 3.0-3.6 V; and TA = TL to TH.
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 25
Electrical Characteristics
2 3
This parameter is supplied for reference and is guaranteed by design and tested. The delay, and the rise and fall, are measured to 20% or 80% of the respective signal. 4 Out delay is shown in Figure 4. Add a maximum of one system clock to the output delay for delay with respect to system clock. 5 This parameter is guaranteed by characterization before qualification rather than 100% tested.
VDD / 2 Pad internal data input signal
Rising-edge out delay
Falling-edge out delay VOH
Pad output
VOL
Figure 4. Pad Output Delay
3.13
3.13.1
Spec 1 2 3 4
1
AC Timing
Reset and Configuration Pin Timing
Table 19. Reset and Configuration Pin Timing1
Characteristic RESET pulse width RESET glitch detect pulse width PLLCFG, BOOTCFG, WKPCFG, RSTCFG setup time to RSTOUT valid PLLCFG, BOOTCFG, WKPCFG, RSTCFG hold time from RSTOUT valid Symbol tRPW tGPW tRCSU tRCH Min 10 2 10 0 Max -- -- -- -- Unit tCYC tCYC tCYC tCYC
Reset timing specified at: FSYS = 132 MHz; VDDEH = 3.0-5.25 V; VDD = 1.35-1.65 V; and TA = TL to TH.
MPC5553 Microcontroller Data Sheet, Rev. 2.0 26 Freescale Semiconductor
Electrical Characteristics
2 RESET 1
RSTOUT
3 PLLCFG BOOTCFG RSTCFG WKPCFG 4
Figure 5. Reset and Configuration Pin Timing
3.13.2
Spec 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1
IEEE 1149.1 Interface Timing
Table 20. JTAG Pin AC Electrical Characteristics1
Characteristic Symbol tJCYC tJDC tTCKRISE tTMSS, tTDIS tTMSH, tTDIH tTDOV tTDOI tTDOHZ tJCMPPW tJCMPS tBSDV tBSDVZ tBSDHZ tBSDST tBSDHT Min 100 40 -- 5 25 -- 0 -- 100 40 -- -- -- 50 50 Max -- 60 3 -- -- 20 -- 20 -- -- 50 50 50 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
TCK cycle time TCK clock pulse width (measured at VDDE / 2) TCK rise and fall times (40% to 70%) TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO data invalid TCK low to TDO high impedance JCOMP assertion time JCOMP setup time to TCK low TCK falling-edge to output valid TCK falling-edge to output valid out of high impedance TCK falling-edge to output high impedance (Hi-Z) Boundary scan input valid to TCK rising-edge TCK rising-edge to boundary scan input invalid
These specifications apply to JTAG boundary scan only. JTAG timing specified at VDD = 1.35-1.65 V, VDDE = 3.0-3.6 V, VDD33 and VDDSYN = 3.0-3.6 V, TA = TL to TH, and CL = 30 pF with DSC = 0b10, SRC = 0b11. Refer to Table 21 for functional specifications.
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 27
Electrical Characteristics
TCK 2 3 2
1
3
Figure 6. JTAG Test Clock Input Timing
TCK
4 5
TMS, TDI
6 7 8
TDO
Figure 7. JTAG Test Access Port Timing
MPC5553 Microcontroller Data Sheet, Rev. 2.0 28 Freescale Semiconductor
Electrical Characteristics
TCK
10 JCOMP
9
Figure 8. JTAG JCOMP Timing
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 29
Electrical Characteristics
TCK
11
13
Output signals
12
Output signals
14 15
Input signals
Figure 9. JTAG Boundary Scan Timing
MPC5553 Microcontroller Data Sheet, Rev. 2.0 30 Freescale Semiconductor
Electrical Characteristics
3.13.3
Spec 1 2 3 4 5 6 7 8 9 10 11
Nexus Timing
Table 21. Nexus Debug Port Timing1
Characteristic Symbol tMCYC tMDC
3 3
Min 12 40 -1.5 -1.5 -1.5 4.0 1 4
4
Max 8 60 3.0 3.0 3.0 -- -- -- 60 -- --
Unit tCYC % ns ns ns tTCYC tMCYC tCYC % ns ns
MCKO cycle time MCKO duty cycle MCKO low to MDO data valid
tMDOV tMSEOV tEVTOV tEVTIPW tEVTOPW tTCYC tTDC tNTDIS, tNTMSS tNTDIH, tNTMSH tJOV
MCKO low to MSEO data valid MCKO low to EVTO data valid EVTI pulse width EVTO pulse width TCK cycle time TCK duty cycle TDI, TMS data setup time TDI, TMS data hold time TCK low to TDO data valid
3
40 8 5
12
VDDE = 2.25-3.0 V VDDE = 3.0-3.6 V RDY valid to MCKO5 --
0 0 --
12 9 --
ns ns --
13
1
2 3 4 5
JTAG specifications apply when used for debug functionality. All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified at VDD = 1.35-1.65 V, VDDE = 2.25-3.6 V, VDD33 and VDDSYN = 3.0-3.6 V, TA = TL to TH, and CL = 30 pF with DSC = 0b10. The Nexus AUX port runs up to 82 MHz. Set NPC_PCR[MCKO_DIV] to divide-by-two if the system frequency is greater than 82 MHz. MDO, MSEO, and EVTO data is held valid until the next MCKO low cycle occurs. Limit the maximum frequency to approximately 16 MHz (VDDE = 2.25-3.0 V) or 22 MHz (VDDE = 3.0-3.6 V) to meet the timing specification for tJOV of [0.2 x tJCYC] as outlined in the IEEE-ISTO 5001-2003 specification. The RDY pin timing is asynchronous to MCKO. The timing is guaranteed by design to function correctly.
1 2 MCKO
4 5 MDO MSEO EVTO
3
Output Data Valid
Figure 10. Nexus Output Timing
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 31
Electrical Characteristics
TCK
10 11
TMS, TDI
12
TDO
Figure 11. Nexus TDI, TMS, TDO Timing
3.13.4
External Bus Interface (EBI) Timing
Table 22. Bus Operation Timing1
Characteristic and Description 40 MHz (ext. bus)2 Min TC tCDC tCRT tCFT 25.0 45% -- -- Max -- 55% --
3
Spec
Symbol
56 MHz (ext. bus)2 Min 17.9 45% -- -- Max -- 55% --
3
66 MHz (ext. bus)2 Min 15.2 45% -- -- Max -- 55% --
3
Unit
Notes
1 2 3 4
CLKOUT period CLKOUT duty cycle CLKOUT rise time CLKOUT fall time
ns TC ns ns
Signals are measured at 50% VDDE.
--3
--3
--3
MPC5553 Microcontroller Data Sheet, Rev. 2.0 32 Freescale Semiconductor
Electrical Characteristics
Table 22. Bus Operation Timing1 (continued)
Characteristic and Description CLKOUT positive edge to output signal invalid or Hi-Z (hold time) External bus interface ADDR[8:31] BDIP CS[0:3] DATA[0:31] OE RD_WR TA TEA TS WE/BE[0:3] Calibration bus interface CAL_ADDR[10:11, 27:30] CAL_CS[0, 2:3] CAL_DATA[0:15] CAL_WE/BE[0:1] tCCOH 1.05 -- 1.5 1.5 1.04 -- 1.5 1.04 -- ns EBTS=1 Hold time selectable via SIU_ECCR[EBTS] bit. tCOV -- 11.0 10.04 -- 8.5 7.54 -- 7.0 EBTS=1 Output valid time selectable via SIU_ECCR[EBTS] bit. 6.04 ns EBTS=0 40 MHz (ext. bus)2 Min tCOH 1.0
4
Spec
Symbol
56 MHz (ext. bus)2 Min 1.04 Max -- 1.5
66 MHz (ext. bus)2 Min 1.04 -- 1.5 Max
Unit
Notes
Max --
EBTS=0 ns EBTS=1 Hold time selectable via SIU_ECCR[EBTS] bit.
1.5
5
EBTS=0
CLKOUT positive edge to output signal valid (output delay) External bus interface ADDR[8:31] BDIP CS[0:3] DATA[0:31] OE RD_WR TA TEA TS WE/BE[0:3] CLKOUT positive edge to output signal valid (output delay) 6a Calibration bus interface CAL_ADDR[10:11, 27:30] CAL_CS[0, 2:3] CAL_DATA[0:15] CAL_WE/BE[0:1]
6
tCCOV --
11.04 -- 12.0
8.54 -- 9.5
7.04 8.0
ns
EBTS=0 EBTS=1 Output valid time selectable via SIU_ECCR[EBTS] bit.
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 33
Electrical Characteristics
Table 22. Bus Operation Timing1 (continued)
Characteristic and Description Input signal valid to CLKOUT positive edge (setup time) External bus interface ADDR[8:31] BDIP DATA[0:31] OE RD_WR TA TEA TS WE/BE[0:3] Input signal valid to CLKOUT positive edge (setup time) 7a Calibration bus interface CAL_ADDR[10:11, 27:30] CAL_CS[0, 2:3] CAL_DATA[0:15] CAL_WE/BE[0:1] CLKOUT positive edge to input signal invalid (hold time) External bus interface ADDR[8:31] BDIP DATA[0:31] OE RD_WR TA TEA TS WE/BE[0:3] Calibration bus interface CAL_ADDR[10:11, 27:30] CAL_CS[0, 2:3] CAL_DATA[0:15] CAL_WE/BE[0:1]
1 2 3 4 5
Spec
Symbol
40 MHz (ext. bus)2 Min Max
56 MHz (ext. bus)2 Min Max
66 MHz (ext. bus)2 Min Max
Unit
Notes
7
tCIS
10.0
--
7.0
--
5.0
--
ns
tCCIS
11.0
--
8.0
--
6.0
--
ns
tCIH
1.0
--
1.0
--
1.0
--
ns
8
tCCIH
1.0
--
1.0
--
1.0
--
ns
EBI timing specified at VDD = 1.35-1.65 V, VDDE = 1.6-3.6 V (unless stated otherwise), VDD33 and VDDSYN = 3.0-3.6 V, TA = TL to TH, and CL = 30 pF with DSC = 0b10. The external bus is limited to half the speed of the internal bus. Refer to fast pad timing in Table 17 and Table 18 (different values for 1.8 V and 3.3 V). The EBTS = 0 timings are tested and valid at VDDE = 2.25-3.6 V only, whereas EBTS = 1 timings are tested and valid at VDDE = 1.6-3.6 V. The EBTS = 0 timings are tested and valid at VDDE = 2.25-3.6 V only, whereas EBTS = 1 timings are tested and valid at VDDE = 1.6-3.6 V.
MPC5553 Microcontroller Data Sheet, Rev. 2.0 34 Freescale Semiconductor
Electrical Characteristics
Voh_f VDDE / 2 CLKOUT Vol_f 3 2 2 4 1
Figure 12. CLKOUT Timing
CLKOUT
VDDE / 2
6 5 5 VDDE / 2
Output bus
VDDE / 2
6 5 5 Output signal
VDDE / 2
6 Output signal
VDDE / 2
Figure 13. Synchronous Output Timing
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 35
Electrical Characteristics
CLKOUT
VDDE / 2
7 8
Input bus
VDDE / 2
7 8
Input signal
VDDE / 2
Figure 14. Synchronous Input Timing
MPC5553 Microcontroller Data Sheet, Rev. 2.0 36 Freescale Semiconductor
Electrical Characteristics
3.13.5
Spec 1 2 3
1
External Interrupt Timing (IRQ Signals)
Table 23. External Interrupt Timing1
Characteristic Symbol tIPWL TIPWH
2
Min 3 3 6
Max -- -- --
Unit tCYC tCYC tCYC
IRQ pulse-width low IRQ pulse-width high IRQ edge-to-edge time
tICYC
IRQ timing specified at FSYS = 132 MHz, VDD = 1.35-1.65 V, VDDEH = 3.0-5.5 V, VDD33 and VDDSYN = 3.0-3.6 V, TA = TL to TH, and CL = 200pF with SRC = 0b11. 2 Applies when IRQ signals are configured for rising-edge or falling-edge events, but not both.
IRQ
1 3
2
Figure 15. External Interrupt Timing
CLKOUT
4
IRQ
Figure 16. External Interrupt Setup Timing
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 37
Electrical Characteristics
3.13.6
Spec 1 2
1
eTPU Timing
Table 24. eTPU Timing1
Characteristic Symbol tICPW tOCPW Min 4 2 Max -- -- Unit tCYC tCYC
eTPU input channel pulse width eTPU output channel pulse width
eTPU timing specified at FSYS = 132 MHz, VDD = 1.35-1.65 V, VDDEH = 3.0-5.5 V, VDD33 and VDDSYN = 3.0-3.6 V, TA = TL to TH, and CL = 200 pF with SRC = 0b11.
2
eTPU output
eTPU input and TCRCLK
1
Figure 17. eTPU Timing
CLKOUT
4
eTPU output
3
eTPU input and TCRCLK
Figure 18. eTPU Input/Output Timing
MPC5553 Microcontroller Data Sheet, Rev. 2.0 38 Freescale Semiconductor
Electrical Characteristics
3.13.7
Spec 1 2
1
eMIOS (MTS) Timing
Table 25. MTS Timing1
Characteristic eMIOS (MTS) input pulse width eMIOS (MTS) output pulse width Symbol tMIPW tMOPW Min 4 1 Max -- -- Unit tCYC tCYC
MTS timing specified at FSYS = 132 MHz, VDD = 1.35-1.65 V, VDDEH = 3.0-5.5 V, VDD33 and VDDSYN = 3.0-3.6 V, TA = TL to TH, and CL = 50 pF with SRC = 0b11.
3.13.8
DSPI Timing
Table 26. DSPI Timing1
80 MHz 112 MHz Min 17.9 ns 15 14 -- -- -- 4 5 20 2 3 20 -4 7 14 -4 -- -- -- -- -5 5.5 4 -5 Max 2.0 ms -- -- -- 25 25 -- -- -- -- -- -- -- -- -- -- 5 25 14 5 -- -- -- -- 132 MHz Unit Min Max 2.9 ms -- -- Min 15.2 ns 13 12 -- -- -- 4 5 20 2 6 20 -4 7 12 -4 -- -- -- -- -5 5.5 3 -5 Max 1.7 ms -- -- -- 25 25 -- -- -- -- -- -- -- -- -- -- 5 25 13 5 -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 25 ns 23 22
Spec 1 2 3 4 5 6 7 8
Characteristic SCK cycle time2,3 PCS to SCK After SCK delay4 delay5
Symbol tSCK tCSC tASC tSDC tA tDIS tPCSC tPASC tSUI 20 2 -4 20 tHI -4 7 21 -4 tSUO -- -- -- -- tHO -5 5.5 8 -5 -- -- -- -- 5 25 18 5 -- -- -- -- -- -- -- --
SCK duty cycle Slave access time (SS active to SOUT driven) Slave SOUT disable time (SS inactive to SOUT Hi-Z, or invalid) PCSx to PCSS time PCSS to PCSx time Data setup time for inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)6 Master (MTFE = 1, CPHA = 1) Data hold time for inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)6 Master (MTFE = 1, CPHA = 1) Data valid (after SCK edge) Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) Data hold time for outputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1)
(tSCK / 2) (tSCK / 2) - 2 ns + 2 ns -- -- 4 5 25 25 -- --
9
10
11
12
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 39
Electrical Characteristics
1
2 3 4 5 6
All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad types of S or SH have an additional delay based on the slew rate. DSPI timing is specified at VDD = 1.35-1.65 V, VDDEH = 3.0-5.5 V, VDD33 and VDDSYN = 3.0-3.6 V, TA = TL to TH, and CL = 50 pF with SRC = 0b11. The minimum SCK cycle time restricts the baud rate selection for the given system clock rate. These numbers are calculated based on two MPC55xx devices communicating over a DSPI link. The actual minimum SCK cycle time is limited by pad performance. The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. This number is calculated using the SMPL_PT bit field in DSPI_MCR set to 0b10.
2 PCSx 4 SCK output (CPOL=0) 4 1
3
SCK output (CPOL=1) 9 SIN 10 Data 12 SOUT First data Data Last data 11 Last data
First data
Figure 19. DSPI Classic SPI Timing--Master, CPHA = 0
MPC5553 Microcontroller Data Sheet, Rev. 2.0 40 Freescale Semiconductor
Electrical Characteristics
PCSx
SCK output (CPOL=0) 10 SCK output (CPOL=1) 9 SIN First data 12 SOUT First data Data Data Last data 11 Last data
Figure 20. DSPI Classic SPI Timing--Master, CPHA = 1
2 SS 1 SCK input (CPOL=0) 4 SCK input (CPOL=1) 5 SOUT First data 9 SIN 10 Data 12 Data 11 4
3
6
Last data
First data
Last data
Figure 21. DSPI Classic SPI Timing--Slave, CPHA = 0
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 41
Electrical Characteristics
SS
SCK input (CPOL=0)
SCK input (CPOL=1) 5 SOUT
11 12 First data 9 10 Data Last data Data Last data 6
SIN
First data
Figure 22. DSPI Classic SPI Timing--Slave, CPHA = 1
3 PCSx 4 2 SCK output (CPOL=0) SCK output (CPOL=1) 9 SIN First data 12 SOUT First data Data Data 11 Last data Last data 4 1
10
Figure 23. DSPI Modified Transfer Format Timing--Master, CPHA = 0
MPC5553 Microcontroller Data Sheet, Rev. 2.0 42 Freescale Semiconductor
Electrical Characteristics
PCSx
SCK output (CPOL=0)
SCK output (CPOL=1) 9 SIN First data Data 12 SOUT First data Data 10
Last data 11 Last data
Figure 24. DSPI Modified Transfer Format Timing--Master, CPHA = 1
SS
2 1
3
SCK input (CPOL=0) 4 SCK input (CPOL=1) 5 SOUT First data 9 SIN First data Data Data 11 12 Last data 10 Last data 6 4
Figure 25. DSPI Modified Transfer Format Timing--Slave, CPHA =0
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 43
Electrical Characteristics
SS
SCK input (CPOL=0)
SCK input (CPOL=1) 5 SOUT
11 12 First data 9 10 Data Last data Data Last data 6
SIN
First data
Figure 26. DSPI Modified Transfer Format Timing--Slave, CPHA =1
7 PCSS PCSx 8
Figure 27. DSPI PCS Strobe (PCSS) Timing
MPC5553 Microcontroller Data Sheet, Rev. 2.0 44 Freescale Semiconductor
Electrical Characteristics
3.13.9
eQADC SSI Timing
Table 27. EQADC SSI Timing Characteristics (Pads at 3.3 V or 5.0 V)
CLOAD = 25 pF on all outputs. Pad drive strength set to maximum. Spec 2 3 4 5 6 7 8
1
Rating FCK period (tFCK = 1 / fFCK) 1, 2 Clock (FCK) high time Clock (FCK) low time SDS lead / lag time SDO lead / lag time EQADC data setup time (inputs) EQADC data hold time (inputs)
Symbol tFCK tFCKHT tFCKLT tSDS_LL tSDO_LL tEQ_SU tEQ_HO
Minimum 2 tSYS_CLK - 6.5 tSYS_CLK - 6.5 -7.5 -7.5 22 1
Typical -- -- -- -- -- -- --
Maximum 17 9 x (tSYS_CLK + 6.5) 8 x (tSYS_CLK + 6.5) +7.5 +7.5 -- --
Unit tSYS_CLK ns ns ns ns ns ns
SS timing specified at FSYS = 132 MHz, VDD = 1.35-1.65 V, VDDEH = 3.0-5.5 V, VDD33 and VDDSYN = 3.0-3.6 V, TA = TL to TH, and CL = 50 pF with SRC = 0b11. Maximum operating frequency varies depending on track delays, master pad delays, and slave pad delays. 2 FCK duty is not 50% when it is generated through the division of the system clock by an odd number.
2 3 FCK 5 SDS 25th 1st (MSB) 2nd 26th 4 4
6 SDO External device data sample at FCK falling-edge 8 7 SDI EQADC data sample at FCK rising-edge 1st (MSB) 2nd
5
25th
26th
Figure 28. EQADC SSI Timing
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 45
Electrical Characteristics
3.14
Fast Ethernet AC Timing Specifications
Media Independent Interface (MII) Fast Ethernet Controller (FEC) signals use transistor-to-transistor logic (TTL) signal levels compatible with devices operating at 3.3 V. The timing specifications for the MII FEC signals are independent of the system clock frequency (part speed designation).
3.14.1
MII FEC Receive Signal Timing FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and FEC_RX_CLK
The receive functions correctly up to an FEC_RX_CLK maximum frequency of 25 MHz plus one percent. There is no minimum frequency requirement. The processor clock frequency must exceed four times the FEC_RX_CLK frequency. Table 28 lists MII FEC receive channel timings.
Table 28. MII FEC Receive Signal Timing
Spec 1 2 3 4 Characteristic FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold FEC_RX_CLK pulse-width high FEC_RX_CLK pulse-width low Min 5 5 35% 35% Max -- -- 65% 65% Unit ns ns FEC_RX_CLK period FEC_RX_CLK period
Figure 29 shows MII FEC receive signal timings listed in Table 28.
M3
FEC_RX_CLK (input)
FEC_RXD[3:0] (inputs) FEC_RX_DV FEC_RX_ER M1 M2
M4
Figure 29. MII FEC Receive Signal Timing Diagram
MPC5553 Microcontroller Data Sheet, Rev. 2.0 46 Freescale Semiconductor
Electrical Characteristics
3.14.2
MII FEC Transmit Signal Timing FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, FEC_TX_CLK
The transmitter functions correctly up to the FEC_TX_CLK maximum frequency of 25 MHz plus one percent. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the FEC_TX_CLK frequency. The transmit outputs (FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER) can be programmed to transition from either the rising- or falling-edge of TX_CLK, and the timing is the same in either case. These options allow the use of non-compliant MII PHYs. Refer to the Fast Ethernet Controller (FEC) chapter of the device reference manual for details of this option and how to enable it. Table 29 lists MII FEC transmit channel timings.
Table 29. MII FEC Transmit Signal Timing
Spec 5 6 7 8 Characteristic FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid FEC_TX_CLK pulse-width high FEC_TX_CLK pulse-width low Min 5 -- 35% 35% Max -- 25 65% 65% Unit ns ns FEC_TX_CLK period FEC_TX_CLK period
Figure 30 shows MII FEC transmit signal timings listed in Table 29.
M7
FEC_TX_CLK (input) M5 FEC_TXD[3:0] (outputs) FEC_TX_EN FEC_TX_ER M6 M8
Figure 30. MII FEC Transmit Signal Timing Diagram
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 47
Electrical Characteristics
3.14.3
MII FEC Asynchronous Inputs Signal Timing FEC_CRS and FEC_COL
Table 30. MII FEC Asynchronous Inputs Signal Timing
Table 30 lists MII FEC asynchronous input signal timing.
Spec 9
Characteristic FEC_CRS, FEC_COL minimum pulse width
Min 1.5
Max --
Unit FEC_TX_CLK period
Figure 31 shows MII FEC asynchronous input timing listed in Table 30.
FEC_CRS, FEC_COL M9
Figure 31. MII FEC Asynchronous Inputs Timing Diagram
3.14.4
MII FEC Serial Management Channel Timing FEC_MDIO and FEC_MDC
Table 31 lists MII FEC serial management channel timings. The FEC functions correctly with a maximum FEC_MDC frequency of 2.5 MHz.
Table 31. MII FEC Serial Management Channel Timing
Spec 10 11 12 13 14 15 Characteristic FEC_MDC falling-edge to FEC_MDIO output invalid (minimum propagation delay) FEC_MDC falling-edge to FEC_MDIO output valid (maximum propagation delay) FEC_MDIO (input) to FEC_MDC rising-edge setup FEC_MDIO (input) to FEC_MDC rising-edge hold FEC_MDC pulse-width high FEC_MDC pulse-width low Min 0 -- 10 0 40% 40% Max -- 25 -- -- 60% 60% Unit ns ns ns ns FEC_MDC period FEC_MDC period
Figure 32 shows MII FEC serial management channel timings listed in Table 31.
MPC5553 Microcontroller Data Sheet, Rev. 2.0 48 Freescale Semiconductor
Electrical Characteristics
M14 M15
FEC_MDC (output)
M10
FEC_MDIO (output)
M11
FEC_MDIO (input)
M12
M13
Figure 32. MII FEC Serial Management Channel Timing Diagram
CLKOUT
5
5
RESET
6
6
RSTOUT
Figure 33. Reset and Configuration Pin Timing
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 49
Mechanicals
4
4.1
4.1.1
Mechanicals
Pinouts
MPC5553 416 PBGA Pinout
Figure 34, Figure 35, and Figure 36 show the pinout for the MPC5553 416 PBGA package. While the MPC5553 and the MPC5554/MPC5565/MPC5566 are pin-compatible, the MPC5553 BGA is shown to highlight the balls that are not connected to any signal on the MPC5553 (the eTPUB[0:31] and TSIZ[0:1]). The alternate Fast Ethernet Controller (FEC) signals that are multiplexed with the data bus are not shown for the MPC5553. NOTE Some pins have names that include functions that are not available on all MPC55xx devices. For example, ball R25 of the 416 BGA package is named `SINA,' but the MPC5553 does not have a DSPI A module. In this case, the SINA pin can only be used for its alternate functions of GPIO[94] or PCSC[2]. Refer to the specific device Reference Manual for functions available on each device.
MPC5553 Microcontroller Data Sheet, Rev. 2.0 50 Freescale Semiconductor
Mechanicals
1 A B VSS VDD 2 VSTBY VSS VDD 3 AN37 AN36 VSS VDD 4 AN11 AN39 AN8 VSS VDD 5 VDDA1 AN19 AN17 AN38 6 AN16 AN20 VSSA1 AN9 7 AN1 AN0 AN21 AN10 8 AN5 AN4 AN3 AN18 9 VRH REF BYPC AN7 AN2 10 AN23 AN22 VRL AN6 11 AN27 AN26 AN25 AN24 12 AN28 AN31 AN30 AN29 13 AN35 AN32 AN33 14 VSSA0 VSSA0 VDDA0 15 AN15 AN14 AN13 16 ETRIG 1 ETRIG 0 NC_9 17 NC_1 NC_5 18 NC_2 NC_6 19 NC_3 NC_7 20 NC_4 21 GPIO 205 22 23 24 VDD MDO0 VSS VDDE7 TMS 25 VDD33 VSS VDDE7 TCK TDO EVTI GPIO 204 26 VSS A
MDO11 MDO8 MDO4 MDO1 VSS VDDE7
NC_8 MDO10 MDO7 MDO6 MDO3
VDDE7 B VDD TDI TEST C D E
C VDD33 D
NC_10 NC_11 NC_12 MDO9
ETPUA ETPUA 30 31
AN34 VDDEH AN12 9
NC_13 NC_14 NC_15 NC_16 MDO5
MDO2 VDDEH 8
ETPUA ETPUA VDDEH E 28 29 1 F G
ETPUA ETPUA ETPUA VDDEH 24 27 26 1 ETPUA ETPUA ETPUA ETPUA 23 22 25 21
MSEO0 JCOMP MSEO1 MCKO
EVTO F NC_17 G
ETPUA ETPUA ETPUA ETPUA H 20 19 18 17 J K ETPUA ETPUA ETPUA ETPUA 16 15 14 13 ETPUA ETPUA ETPUA ETPUA 12 11 10 9 VSS VSS
Version 2.1 - 13 July 2004
RDY
GPIO 203
NC_18 NC_19 H
VDDEH NC_20 NC_21 NC_22 J 6 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDE7 VDDE7 VDDE7 VDDE7 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDE7 VDDE7 VDDE7 VSS VSS VSS VSS NC_23 NC_24 NC_25 NC_26 K NC_27 NC_28 NC_29 NC_30 L NC_31 NC_32 NC_33 SINB M
ETPUA ETPUA ETPUA ETPUA L 8 7 6 5 M N P R ETPUA ETPUA ETPUA ETPUA 4 3 2 1 BDIP CS3 WE3 TEA CS2 WE2 ETPUA TCRCLK 0 A CS1 WE1 CS0 WE0
VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VSS VSS
SOUTB PCSB3 PCSB0 PCSB1 N PCSA3 PCSB4 SCKB PCSB2 P PCSB5 SOUTA SINA SCKA R VPP T
T VDDE2 NC_34 RD_WR VDDE2 ADDR U NC_35 16 V W Y ADDR 18 ADDR 20 ADDR 22 ADDR 17 ADDR 19 ADDR 21 ADDR 23 ADDR 25 ADDR 27 ADDR 30 VSS VDD 2 TA TS ADDR 9 VDD33 ADDR 8 ADDR 10
VDDE2 VDDE2 VDDE2 VDDE2
PCSA1 PCSA0 PCSA2
VDDE2 VDDE2 VDDE2 VDDE2 VDDE2
PCSA4 TXDA PCSA5 VFLASH U CNTXC RXDA RSTOUT RST CFG V
ADDR VDDE2 11 ADDR 13 ADDR 15 ADDR 31 VSS VDD DATA 16 3 ADDR 12 ADDR 14 VSS VDD DATA 17 DATA 18 4 VDD DATA 24 DATA 19 VDDE2 5 DATA 26 DATA 25 DATA 21 DATA 20 6 DATA 28 DATA 27 DATA 23 DATA 22 7 VDDE2 DATA 29 DATA 0 GPIO 206 8
Note:
NC_X NC_36
No connects (x = 1 to 38)
NC_37
RXDB CNRXC TXDB RESET W WKP CFG BOOT CFG1 VRC VSS VSS SYN Y
ADDR AA 24 AB VDDE2 ADDR AC 26 AD AE AF ADDR 28 ADDR 29 VSS 1
No connect. AC22 & AD23 reserved
VDDEH PLL 6 CFG1 VDD VRC CTL VDD VSS
BOOT EXTAL AA CFG0 PLL CFG0 VRC33 VDD XTAL VDD SYN AB AC
DATA 30 VDD33 DATA 2 DATA 1 9
DATA 31 GPIO 207 DATA 4 DATA 3 10
DATA 8 DATA 9 DATA 6 VDDE2 11
DATA 10 DATA 11 OE DATA 5 12
VDDE2 DATA 13 BR DATA 7 13
DATA 12 DATA 15 BG
DATA 14
EMIOS EMIOS EMIOS EMIOS VDDEH VDDE5 NC_36 2 8 12 21 4
VSS
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 NC_37 3 6 10 15 17 22
VDD33 AD VDD VSS 26 AE AF
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS 1 5 9 13 16 19 23 ENG CLK 25
NC_38 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5 0 4 7 11 14 18 20 14 15 16 17 18 19 20 21 22 23 24
Figure 34. MPC5553 416 Package
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 51
Mechanicals
1 A B VSS VDD 2 VSTBY VSS VDD 3 AN37 AN36 VSS VDD 4 AN11 AN39 AN8 VSS VDD 5 VDDA1 AN19 AN17 AN38 6 AN16 AN20 VSSA1 AN9 7 AN1 AN0 AN21 AN10 8 AN5 AN4 AN3 AN18 9 VRH REF BYPC AN7 AN2 10 AN23 AN22 VRL AN6 11 AN27 AN26 AN25 AN24 12 AN28 AN31 AN30 AN29 13 AN35 AN32 AN33 AN34
C VDD33 D E F G H J K L M N P R
ETPUA ETPUA 30 31
ETPUA ETPUA VDDEH 28 29 1
ETPUA ETPUA ETPUA VDDEH 24 27 26 1 ETPUA ETPUA ETPUA ETPUA 23 22 25 21 ETPUA ETPUA ETPUA ETPUA 20 19 18 17 ETPUA ETPUA ETPUA ETPUA 16 15 14 13 ETPUA ETPUA ETPUA ETPUA 12 11 10 9 ETPUA ETPUA ETPUA ETPUA 8 7 6 5 ETPUA ETPUA ETPUA ETPUA 4 3 2 1 BDIP CS3 WE3 TEA CS2 WE2 ETPUA TCRCLK 0 A CS1 WE1 CS0 WE0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Version 2.1 - 13 July 2004
VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VSS VSS
T VDDE2 NC_34 RD_WR VDDE2 U V W Y ADDR NC_35 16 ADDR 18 ADDR 20 ADDR 22 ADDR 17 ADDR 19 ADDR 21 ADDR 23 ADDR 25 ADDR 27 ADDR 30 VSS VDD 2 TA TS ADDR 9 VDD33 ADDR 8 ADDR 10
VDDE2 VDDE2
VDDE2 VDDE2 VDDE2
Note:
NC_X
No connects (x = 1 to 38) No connect. AC22 & AD23 reserved
ADDR VDDE2 11 ADDR 13 ADDR 15 ADDR 31 VSS VDD DATA 16 3 ADDR 12 ADDR 14 VSS VDD DATA 17 DATA 18 4 VDD DATA 24 DATA 19 VDDE2 5
NC_36 NC_37
ADDR AA 24 AB VDDE2 AC AD AE AF ADDR 26 ADDR 28 ADDR 29 VSS 1
DATA 26 DATA 25 DATA 21 DATA 20 6
DATA 28 DATA 27 DATA 23 DATA 22 7
VDDE2 DATA 30 DATA 29 DATA 0 GPIO 206 8 VDD33 DATA 2 DATA 1 9
DATA 31 GPIO 207 DATA 4 DATA 3 10
DATA 8 DATA 9 DATA 6
DATA 10 DATA 11 OE
VDDE2 DATA 13 BR DATA 7 13
VDDE2 DATA 5 11 12
Figure 35. MPC5553 416 Package, Left Side
MPC5553 Microcontroller Data Sheet, Rev. 2.0 52 Freescale Semiconductor
Mechanicals
14 VSSA0 VSSA0 VDDA0
15 AN15 AN14 AN13
16 ETRIG 1 ETRIG 0 NC_9
17 NC_1 NC_5
18 NC_2 NC_6
19 NC_3 NC_7
20 NC_4
21
22
23
24 VDD MDO0 VSS VDDE7 TMS
25 VDD33 VSS VDDE7 TCK TDO EVTI GPIO 204
26 VSS A
GPIO MDO11 MDO8 205 MDO4 MDO1 VSS VDDE7
NC_8 MDO10 MDO7 MDO6 MDO3
VDDE7 B VDD TDI TEST EVTO C D E F
NC_10 NC_11 NC_12 MDO9
VDDEH AN12 9
NC_13 NC_14 NC_15 NC_16 MDO5
MDO2 VDDEH 8
MSEO0 JCOMP MSEO1 MCKO RDY GPIO 203
NC_17 G
NC_18 NC_19 H
VDDEH NC_20 NC_21 NC_22 J 6 VDDE7 VDDE7 VDDE7 VDDE7 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDE7 VDDE7 VDDE7 VSS VSS VSS VSS NC_23 NC_24 NC_25 NC_26 K NC_27 NC_28 NC_29 NC_30 L NC_31 NC_32 NC_33 SINB M
SOUTB PCSB3 PCSB0 PCSB1 N PCSA3 PCSB4 SCKB PCSB2 P PCSB5 SOUTA SINA SCKA R VPP T
VDDE2 VDDE2 VDDE2 VDDE2
PCSA1 PCSA0 PCSA2
PCSA4 TXDA PCSA5 VFLASH U CNTXC RXDA RSTOUT RST CFG V
RXDB CNRXC TXDB RESET W WKP CFG BOOT CFG1 VRC VSS VSS SYN Y
VDDEH PLL 6 CFG1 VDD DATA 12 DATA 15 BG DATA 14 EMIOS EMIOS EMIOS EMIOS VDDEH VDDE5 NC_36 2 8 12 21 4 VSS VRC CTL VDD VSS
BOOT EXTAL AA CFG0 PLL CFG0 VRC33 VDD XTAL VDD SYN AB AC
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 NC_37 3 6 10 15 17 22
VDD33 AD VDD VSS 26 AE AF
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS 1 5 9 13 16 19 23 ENG CLK 25
NC_38 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5 0 4 7 11 14 18 20 14 15 16 17 18 19 20 21 22 23 24
Figure 36. MPC5553 416 Package, Right Side
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 53
Mechanicals
4.1.2
1 A VSS 2 VDD VSS
MPC5553 324 PBGA Pinout
3 VSTBY VDD VSS 4 AN37 AN36 VDD VSS 5 AN11 AN39 AN8 VDD 6 7 8 AN1 AN0 AN21 AN10 9 AN5 AN4 AN3 AN18 10 VRH REF BYPC AN7 AN2 11 VRL AN23 AN22 AN6 12 AN27 AN26 AN25 AN24 13 AN28 AN31 AN30 AN29 14 AN35 AN32 AN33 15 VSSA0 VSSA0 VDDA0 16 17 18 19 20 VDD MDO0 VSS VDDE7 TMS 21 VDD33 VSS VDDE7 TCK TDO EVTI 22 VSS A
Figure 37 is a pinout for the MPC5553 324 PBGA package.
VDDA1 VSSA1 AN19 AN17 AN38 AN16 AN20 AN9 AN12 MDO11 MDO10 MDO8 AN13 AN14 MDO9 MDO5 MDO6 MDO7 MDO2 MDO3 MDO4 MDO1 VSS VDDE7
B VDD33 C D
VDDE7 B VDD TDI TEST EVTO C D E F
ETPUA ETPUA 30 31
ETPUA ETPUA ETPUA 28 29 26
AN34 VDDEH AN15 9
ETPUA ETPUA ETPUA ETPUA E 24 27 25 21 ETPUA ETPUA ETPUA ETPUA F 23 22 17 18 ETPUA ETPUA ETPUA ETPUA G 20 19 14 13 ETPUA ETPUA ETPUA VDDEH H 16 15 10 1 ETPUA ETPUA ETPUA ETPUA J 6 9 12 11 ETPUA ETPUA ETPUA ETPUA K 5 8 7 2 ETPUA ETPUA ETPUA ETPUA L 1 4 3 0 M N P R TCRCLK BDIP A CS3 ADDR 16 ADDR 18 CS2 CS1 WE1 CS0 WE0
VDDE7 JCOMP
Version 2.2p - 13 July 2004
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDE7 VSS VSS VSS VSS VSS
RDY
MCKO MSEO0 MSEO1 G GPIO 204 SINB H
VDDEH GPIO 10 203
SOUTB PCSB3 PCSB0 PCSB1 J PCSA3 PCSB4 SCKB PCSB2 K PCSB5 SOUTA SINA SCKA L VPP M
VDDE2 VDDE2 VSS VSS VSS VSS
PCSA1 PCSA0 PCSA2
PCSA4 TXDA PCSA5 VFLASH N CNTXC RXDA RSTOUT WKP CFG RST CFG P
ADDR RD_WR VDD33 17 ADDR VDDE2 19 ADDR 21 ADDR 23 ADDR 25 ADDR 12 ADDR 13 ADDR 15 TA TS ADDR 14 ADDR 31 VSS VDD VDD
CNRXC TXDB RESET R BOOT CFG1
ADDR T 20 ADDR U 22 V ADDR 24
Note:
NC
No connect. Reserved (W18 & Y19 are shorted to each other)
RXDB
VRC VSS
VSS SYN
T
VDDEH PLL 6 CFG1 VDD VRC CTL VDD VSS
BOOT EXTAL U CFG0 PLL CFG0 VRC33 VDD XTAL VDD SYN V W
ADDR ADDR W VDDE2 30 26 ADDR Y 28 ADDR AA 29 AB VSS 1 ADDR 27 VSS VDD 2 VSS VDD
VDDE2 VDD33 VDDE2 DATA 11 DATA 9 GPIO 206 DATA 4 7 DATA 10 DATA 5 DATA 6 8 GPIO 207 DATA 7 OE 9
DATA 12 DATA 13
DATA 14 DATA 15
EMIOS EMIOS VDDEH EMIOS EMIOS VDDE5 21 4 12 2 8
NC
VSS NC
VDDE2 DATA 8 VDDE2 DATA 3 6
EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 22 17 10 15 6
VDD33 Y VDD VSS 22 AA AB
VDDE2 DATA 1 DATA 2 5
VDDE2 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS 23 19 16 3 5 9 13 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5 20 18 14 0 1 4 7 11 10 11 12 13 14 15 16 17 18 19 20 ENG CLK 21
DATA VDDE2 0 3 4
Figure 37. MPC5553 324 Package
MPC5553 Microcontroller Data Sheet, Rev. 2.0 54 Freescale Semiconductor
Mechanicals
4.1.3
MPC5553 208 MAP BGA Pinout
NOTES VDDEH10 and VDDEH6 are connected internally on the 208-ball package and are listed as VDDEH6.
Figure 38 is a pinout for the MPC55MPC5553 208 MAP BGA package.
1 A B VSS VDD
2 AN9 VSS VDD AN39
3 AN11 AN38 VSS VDD AN37
4
5
6 AN1 AN4 AN16 AN2
7 AN5 REF BYPC AN3 AN6
8 VRH AN22 AN7 AN24
9 VRL AN25 AN23 AN30
10 AN27 AN28 AN32 AN31
11 VSSA0 VDDA0 AN33
12 AN12 AN13 AN14
13 MDO2 MDO3 AN15 VSS VDDE7
14
15
16 VSS VDD TCK TEST A B C D
VDDA1 VSSA1 AN21 AN17 VSS VDD AN36 AN0 AN34 AN18
MDO0 VDD33 MDO1 VSS TMS TDI TDO VSS MSEO0 EVTO EVTI
C VSTBY D VDD33 E F G H J K L M N P R T
AN35 VDDEH 9
ETPUA ETPUA 30 31
MSEO1 E
ETPUA ETPUA ETPUA 28 29 26
8 June 2005p
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VDDEH 6
MCKO JCOMP F SINB PCSB0 G
ETPUA ETPUA ETPUA ETPUA 24 27 25 21 ETPUA ETPUA ETPUA ETPUA 23 22 17 18 ETPUA ETPUA ETPUA ETPUA 14 20 19 13 ETPUA ETPUA ETPUA VDDEH 16 15 7 1 ETPUA ETPUA ETPUA TCRCLK 12 11 6 A ETPUA ETPUA ETPUA ETPUA 1 5 9 10 ETPUA ETPUA ETPUA 0 4 8 ETPUA ETPUA 2 3 CS0 VSS 1 VSS VDD 2 VSS VDD OE 3 VSS VDD GPIO 206 VDD GPIO 207
SOUTB PCSB3
PCSA3 PCSB4 PCSB2 PCSB1 H PCSB5 TXDA PCSA2 SCKB J CNTXC RXDA RSTOUT TXDB CNRXC RXDB PLL CFG0 VRC CTL VSS VDD ENG CLK 14 WKP CFG BOOT CFG1 PLL CFG1 VRC33 VSS VDD 15 VPP K
RESET L VSS SYN M
VDD33 EMIOS EMIOS VDDEH EMIOS EMIOS VDD33 2 10 21 4 12 VDDE2 EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA 6 8 22 16 17
VSS VDD
EXTAL N XTAL VDD SYN VSS 16 P R T
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA CNRXB 4 3 9 11 14 19 23
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB VDDE5 0 1 5 7 13 15 18 20 4 5 6 7 8 9 10 11 12 13
Figure 38. MPC5553 208 Package
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 55
Mechanicals
4.2
4.2.1
Package Dimensions
MPC5553 416-Pin Package
The package drawings of the MPC5553 416 pin TEPBGA package are shown in Figure 39.
Figure 39. MPC5553 416 TEPBGA Package
MPC5553 Microcontroller Data Sheet, Rev. 2.0 56 Freescale Semiconductor
Mechanicals
Figure 39. MPC5553 416 TEPBGA Package (continued)
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 57
Mechanicals
4.2.2
MPC5553 324-Pin Package
The package drawings of the MPC5553 324-pin TEPBGA package are shown in Figure 40.
Figure 40. MPC5553 324 TEPBGA Package
MPC5553 Microcontroller Data Sheet, Rev. 2.0 58 Freescale Semiconductor
Mechanicals
Figure 40. MPC5553 324 TEPBGA Package (continued)
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 59
Mechanicals
4.2.3
MPC5553 208-Pin Package
The package drawings of the MPC5553 208-pin MAP BGA package are shown in Figure 41.
Figure 41. MPC5553 208 MAP BGA Package
MPC5553 Microcontroller Data Sheet, Rev. 2.0 60 Freescale Semiconductor
Mechanicals
Figure 41. MPC5553 208 MAP BGA Package (continued)
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 61
MPC5553 Revision History
5
MPC5553 Revision History
Table 32. MPC5553 Revision History
Revision Rev. 0 Rev. 1 Table 1 Table 2 Figure 39, Figure 40, Figure 41 Figure 37 Rev. 1.1 Throughout Location(s) Substantive Change(s) This is the first released version of this document. Footnote added to Freescale Part Number column. Footnotes 6, 8, and 9 changed from 1mA to 2mA. Second page of package drawings added. Removed note about pin R1 in the figure and added a Note above it instead. Editorial changes: subscripting, simplifying language.
Table 32 provides a revision history of the MPC5553 Data Sheet.
MPC5553 Microcontroller Data Sheet, Rev. 2.0 62 Freescale Semiconductor
MPC5553 Revision History
Table 33 is the new format for the Revision History and changes continue from Table 32.
Table 33. MPC5553 Revision History (continued)
Revision Rev. 1.1 Author NH Date 02/02/07 Substantive Change(s) Changes per RD initial review: * Changed the values in Table 14 for the H7Fa Flash pre-program and erase times. Typical and Initial Max values changed. * Typical Values -- 16 Kbytes: from 265 to 325 48 Kbytes: from 340 to 435 64 Kbytes: from 400 to 525 128 Kbytes: from 500 to 675 * Initial Max Values -- 16 Kbytes: from 400 to 525 48 Kbytes: from 400 to 525 64 Kbytes: from 500 to 675 128 Kbytes: from 1250 to 1800 Changes per RD second review: * Added Figure 3 to show interpolated IDDSTBY values listed in Table 9. * Table 9 DC Electrical Specifications: Changed wording of footnote 3. Spec 28: Corrected conditional text error showing wrong frequency. Spec 29: Deleted frequency information. * Table 6 FMPLL Electrical Characteristics: Grouped (2 x Cl) in Specs 12 and 13. * Table 7 Power Sequence Pin Status for Fast Pads, updated paragraph. * Table 8 Power Sequence Pin Status, updated preceding paragraph. * Section 3.7.1, "Input Value of Pins During POR Dependent on VDD33 Updated paragraph to remove redundancy, * Table 16 Flash BIU Settlings: Changed wording of footnote from "Can be changed after Analysis and Characterization" to "These values may change after characterization." * Table 17and Table 18: Deleted the words `not' from footnote 2. Changed from `This parameter is supplied for reference and is not guaranteed by design and not tested' to `This parameter is supplied for reference and is guaranteed by design and tested.' * Table 22 Bus Operation Timing: Specs 5 and 6: corrected format to show the bus timing values for various frequencies with EBTS bit = 0 and EBTS bit = 1. Specs 6 and 7: Added the calibrations signals: CAL_ADDR, CAL_WE/BE, CAL_CS, CAL_DATA. * Table 26 DSPI Timing: Added to beginning of footnote 1 `All DSPI timing specifications use the fastest slew rate (SRC=0b11) on pad type M or MH. DSPI signals using pad types of S or SH have an additional delay based on the slew rate.' * Table 27 EQADC SS Timing Characteristics: combined footnotes 1 and 2. Moved footnotes 1 and 2 to Spec 2 and deleted Spec 1.
Rev. 1.1
NH
02/06/07
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 63
MPC5553 Revision History
Table 33. MPC5553 Revision History (continued)
Revision Rev 2.0 Author NH Date 02/07/07 Substantive Change(s) Changes per RD sign-off review: * Changed paragraph preceding Table 7 Power Sequence Pin Status for the Fast Pad: From: Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current spikes, etc., the state of the I/O pins during power up/down varies depending on power. Prior to exiting POR, the pads are in a high impedance state (Hi-Z). To: There are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current spikes, and so on. Therefore, the state of the I/O pins during power up/down varies depending on which supplies are powered. * Section 3.7.1, "Input Value of Pins During POR Dependent on VDD33," changed From: To avoid accidentally selecting the bypass clock because PLLCFG[0:1] and RSTCFG are not treated as ones (1s) when POR negates, VDD33 must not lag VDDSYN and the RESET pin power (VDDEH6) when powering the device by more than the VDD33 lag specification in Table 6. VDD33 individually can lag either VDDSYN or the RESET power pin (VDDEH6) by more than the VDD33 lag specification. VDD33 can lag one of the VDDSYN or VDDEH6 supplies, but cannot lag both by more than the VDD33 lag specification. This VDD33 lag specification only applies during power up. VDD33 has no lead or lag requirements when powering down. To: When powering the device, VDD33 must not lag VDDSYN and the RESET power pin (VDDEH6) by more than the VDD33 lag specification listed in Table 6. This avoids accidentally selecting the bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and therefore cannot read the default state when POR negates. VDD33 can lag VDDSYN or the RESET power pin (VDDEH6), but cannot lag both by more than the VDD33 lag specification. This VDD33 lag specification only applies during power up. VDD33 has no lead or lag requirements when powering down. * Table 22 Bus Operation Timing: Added the correct pins to the calibration signals: CAL_ADDR[10:11, 27:30], CAL_WE/BE[0:1], CAL_CS[0, 2:3], and CAL_DATA[0:15]. Added calibration signals to Specs 5 and 8. * Corrected the following EBI signals: Specs 7 and 8: Added the following signals to Specs 7 and 8 the EBI section: OE, RD_WR, and BDIP. Broke out Spec 6 CLKOUT Posedge to output signal valid into Spec 6 for the EBI signals, and Spec 6a for the calibration signals, Broke out Spec 7 Input Signal Valid to CLKOUT Posedge into Spec 7 for the EBI signals, and Spec 7a for the calibration signals. * Section 3.7.3, "Power-Down Sequence (VRC33 Grounded)" Deleted the underscore in ORed_POR to become ORed POR. Table 22 Bus Operation Timing: Removed references to CAL_OE, CAL_RD_WR, and CAL_TS because they really use the EBI signals OE, RD_WR, and TS on the MPC5553.
Rev 2.0
NH
2/09/07
MPC5553 Microcontroller Data Sheet, Rev. 2.0 64 Freescale Semiconductor
MPC5553 Revision History
Table 33. MPC5553 Revision History (continued)
Revision Rev 2.0 Author NH Date 2/27/07 Substantive Change(s) Per RD comments: Table 2 Absolute Maximum Ratings: changed footnote 6 from: Keep the negative DC current greater than 0.6 V on eTPUB[15] and SINB during the internal power-on reset (POR) state. To: Keep the negative DC current greater than -0.6 V on eTPUB[15] and SINB during the internal power-on reset (POR) state. Figure 38 MPC5553 208 Map BGA Pinout: Deleted two lines referring to the CS[0] signal ball assignment for the 208. Corrected the signal names in Section 3.14, "Fast Ethernet AC Timing Specifications" to include the FEC_ prefix for the signal name. Waiting on response from Jim Eifert, Randy Dees, Jeffery Hopkins, and Bill Terry about the following Bugs filed against the Data Sheets: 1474, 1480, 1482, 1483, 1811, 1815, 1884, 2254, 2419, 2717, 2873 before preparing for final sign-off again.
Rev 2.0
NH
3/1/07
MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 65
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